Intel launches 12-core Xeon E5-2600 v2 server chip

Intel Xeon 

Intel has officially launched the Xeon E5-2600 v2 family of processors for two-socket server and workstation systems, offering improved performance with up to 12 cores plus enhancements to memory bandwidth, virtualisation and security.

Launched at the Intel Developer Forum (IDF) in San Francisco, the Xeon E5-2600 v2 is the successor to the existing E5-2600 line based on Sandy Bridge technology, updating it to the 22nm Ivy Bridge core architecture, which brings improvements in single-threaded performance plus a focus on power efficiency, Intel said.

Also known by its codename of Ivy Bridge EP, the Xeon E5-2600 v2 offers up to 50 percent more cores than its predecessor, can be configured with twice the memory (up to 1536GB at 1866MHz), and supports base clock speeds up to 3.5GHz.

Xeon E5-2600 v2 will also ship in a variety of different options for different usage models.These include low-power versions operating as low as 40W; high-frequency, low core count versions; or high core count versions operating at up to 130W for maximum performance.

This fits with Intel's messaging about offering customers choices regarding the best platform for specific workloads in the data centre. In some cases, choosing a 130W chip may make more sense for power efficiency as its 12 cores may lead to fewer servers being required to handle the same workload.

Diane Bryant, Intel senior vice president for the data centre and connected systems group, said "Offering new cloud-based services requires an infrastructure that is versatile enough to support the diverse workloads and is flexible enough to respond to changes in resource demand across servers, storage and network."

Intel said that the Xeon E5-2600 v2 actually comes in three separate die flavours: one for four to six-core chips with 15MB of shared L3 cache, another for six to 10 cores with 25MB L3 cache, and the third for the 12-core chips with 30MB L3 cache, targeting maximum performance.
The 12-core die also features a more complex ring bus arrangement connecting the on-chip components, because the cores here are arranged in three groups rather than two, and boasts an additional memory controller to boost memory bandwidth.

Other enhancements include improved cache snooping to boost performance in....
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